This comprehensive reference, which has been fully updated for the most recent Verilog HDL versions, logically advances from the most basic Verilog ideas to the most cutting-edge digital design methods available today. Written from a practical design standpoint, it provides extensive covering of Verilog HDL for both novices and seasoned students. Samir Palnitkar teaches students how to create complex digital designs of tomorrow by introducing them to concepts such as gate, dataflow (RTL), behavioral, and switch level modeling one step at a time. He also presents the Programming Language Interface (PLI), describes leading logic synthesis methodologies, and explains timing and delay simulation. Palnitkar provides over 300 totally revised pictures, examples, and exercises together with a wealth of tried-and-true Verilog HDL modeling advice. Comprehensive learning goals and handy summaries are included in every chapter.
৳1140 ৳1340-14.93%
- Brand: Pearson
- SKU: 9788177589184
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